The present invention relates to a method and apparatus for implementing error injection for peripheral component interconnect (PCI) bridges.
A peripheral component interconnect (PCI) local bus system often includes a primary 64-bit PCI bus and multiple, such as eight secondary PCI busses. The PCI local bus is a high performance, 32-bit or 64-bit bus with multiplexed address and data lines. The bus is used as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor and memory systems. Typically error recovery paths are the most complicated and the hardest to test in system development.
A mechanism is needed for implementing error injection for peripheral component interconnect (PCI) bridges. There is a need for a repeatable method of injecting errors on different PCI busses for PCI bridges. A need exists for a way of injecting PCI bus errors on all PCI busses associated with a PCI bridge.
A principal object of the present invention is to provide a method and apparatus for implementing error injection for peripheral component interconnect (PCI) bridges. Other important objects of the present invention are to provide such method and apparatus for implementing error injection for peripheral component interconnect (PCI) bridges substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for implementing error injection for peripheral component interconnect (PCI) bridges. The apparatus for implementing error injection for peripheral component interconnect (PCI) bridges includes a plurality of PCI busses and a control logic coupled to the plurality of PCI busses. The control logic targets a selected bus of the plurality of PCI busses. A hit is detected on the selected bus. Responsive to the detected hit, an error is injected on the selected bus.
In accordance with features of the invention, for a detected hit for predefined bug types, the operation must match a selected read or write, target or master, command type and the address must match unmasked address bits. For a detected hit for another predefined bug type, the PCI data bus must also match an unmask data register.